Semiconductor devices typically include a stack of patterned layers formed from a series of processing steps including deposition, lithographic exposure of a desired pattern, and etching exposed or unexposed portions. The exposure step for a given layer is typically divided into a grid of exposure fields such that a lithography tool separately exposes each field.
Lithography overlay represents the alignment error, or misregistration, between two or more layers. Overlay errors may result from varied sources such as systematic bias from fabrication tools, stochastic errors, or sample variations. Further, overlay errors may vary systematically or randomly across a sample for each exposure field. Overlay errors are typically mitigated and/or compensated for during production by tightly controlling the configuration of the lithography tool for each exposure field. For example, the lithography tool may align the reticle to the sample based on measurements of alignment targets already fabricated on the sample. Further, the lithography tool may employ additional overlay corrections based on overlay measurements of overlay targets.
Some control systems may utilize feed-forward data from a reference layer including alignment and/or overlay targets. However, a control system based on both alignment corrections from alignment targets and overlay corrections from overlay targets may produce cross-talk that results in overcorrection and instability, particularly when reference layers for alignment and overlay are the same. Further, typical control systems may not be suitable for advanced overlay control schemes such as those utilizing different types of reference targets from one layer to the next or those utilizing distinct reference layers for each measurement direction.
Therefore, it may be desirable to provide systems and methods for providing stable overlay control for multiple configurations of alignment and overlay reference layers.